The present invention relates, in general, to semiconductor devices and, more particularly, to an internal clock generator for generating an internal clock signal and a method of generating an internal clock.
In general, a semiconductor memory device that performs data input and output operations in synchronization with a clock signal, such as Synchronous Dynamic Random Access Memory (SDRAM), includes an internal clock generator. The internal clock generator generates an internal clock signal based on an external clock signal received from an external device.
FIG. 1 is a circuit diagram of a conventional internal clock generator. Referring to FIG. 1, the internal clock generator 10 includes an input buffer 11, a delay circuit 12 and a clock output unit 13. The clock output unit 13 includes PMOS transistors P1 and P2, NMOS transistors N1 and N2, and an inverter 14. The operational process of the internal clock generator 10 will be described below in short with reference to FIG. 2.
FIG. 2 is a timing diagram showing signals related to the operation of the internal clock generator shown in FIG. 1. The input buffer 11 receives an external clock signal EXCLK and outputs it to the clock output unit 13. The delay circuit 12 delays the external clock signal EXCLK for a set time and outputs a delay clock signal DXCLK. The clock output unit 13 outputs an internal clock signal INCLK in response to the external clock signal EXCLK and the delay clock signal DXCLK. Preferably, whenever both the external clock signal EXCLK and the delay clock signal DXCLK become a high level, the clock output unit 13 outputs the internal clock signal INCLK as a high level. Meanwhile, a pulse width of the external clock signal EXCLK may be changed depending on process, voltage and temperature (hereinafter, referred to as “PVT”). If the pulse width of the external clock signal EXCLK is changed as described above, the pulse width of the internal clock signal INCLK can be changed. In particular, in the internal clock generator 10 that generates the internal clock signal INCLK based on a logic state of the external clock signal EXCLK, the pulse width of the internal clock signal INCLK is significantly influenced by variation in the pulse width of the external clock signal EXCLK. In other words, the narrower the pulse width of the external clock signal EXCLK, the narrower the pulse width of the internal clock signal INCLK, and the wider the pulse width of the external clock signal EXCLK, the wider the pulse width of the internal clock signal INCLK. In general, in the specification of Double Data Rate (DDR) SDRAM, the pulse width of the external clock signal EXCLK is set to a specific value. However, in the specification of SDRAM, there is no special limit to the pulse width of the external clock signal EXCLK. In this case, if the pulse width of the external clock signal EXCLK is reduced excessively, severe SDRAM malfunctions may occur. This is because if the pulse width of the external clock signal EXCLK is reduced excessively, the internal clock generator 10 cannot generate the internal clock signal INCLK. In more detail, for example, if the pulse width of the external clock signal EXCLK is “D1” (that is, a time in which the external clock signal EXCLK is kept to a high level is longer than a delay time of the delay circuit 12), as shown in FIG. 2, the internal clock generator 10 normally generates the internal clock signal INCLK. However, if the pulse width of the external clock signal EXCLK is “D2” (that is, a time in which the external clock signal EXCLK is kept to a high level is shorter than a delay time of the delay circuit 12), there is no period in which the external clock signal EXCLK and the delay clock signal DXCLK are at a high level at the same time. Accordingly, the internal clock generator 10 cannot generate the internal clock signal INCLK. As a result, the internal clock generator 10 cannot keep the pulse width of the internal clock signal INCLK constant if the pulse width of the external clock signal EXCLK is changed.